16. Schematic

A schematic reads a diagram as a circuit sheet: layout: schematic places components and lets the orthogonal router draw the wires — unlike sequence and drawing, the engine never consumes its links (SPEC 11); it places, reinterprets a few link forms, and dresses the result. Wires land on pins — fixed ports the router hits exactly (ROUTING.md, Fixed ports) — bend square, and meet at junction dots. Everything else is the core: a named wire is a link label, the region boxes are |group|s, the sheet is a |page|, the title block ISO 7200 (SPEC 15.8). Its children split by role:

Vocabulary: a component is the part instance; a symbol is the drawing it (or a label) wears — symbol: names one, exactly as on |icon| (SPEC 7). Schematic types are legal only in a schematic scope (SPEC 21); the schematic link laws (16.5) reach links written in nested ordinary containers, but placement never cascades — a nested |row| or |grid| places its own children, exactly as in a drawing.

16.1 Placement — the lattice

The sheet is a grid. A scope places on two pitches. The fine pitch is pin-pitch (SPEC 10.5) — every pin, stub tip and wire track lands on it. The coarse pitch is the scope’s gap, which every part centre lands on: here gap is the column and row pitch, not the space between two tracks, and it rounds up to a whole number of fine pitches, so a part centre is always a wire line too (gap: 120 80 states row and column apart, as gap reads everywhere). Two adjacent anchors with nothing between them stand one coarse column apart, and never closer. Two wired neighbouring pins stand one fine pitch apart, so a scope whose clearance runs past that pitch is an error (SPEC 21) — said once, where the number is written, rather than as a stray for every lead that then finds no track. The finished sheet centres on the scope’s own origin, and that shift is a whole number of fine pitches — so a part placed on the lattice is still on it once the sheet is squared up. The lattice is the scope’s, counted from its own origin, and the router rounds a wire to it wherever the parent seated the scope (ROUTING.md, Track quantum) — a nested sheet stands exactly where its parent put it.

Ink never places. A satellite’s cell comes from the lattice, never from the width of its ref or value: a long value overhangs the column beside it, and gap is the lever. Ink is read only where a count of cells is owed — a field’s origin, the air two neighbouring anchors keep, a label symbol’s reach across the line it stands on — and every such reading rounds onto the lattice. So a part’s text can hold a field or a track one cell wider, and never says which cell another part takes.

A satellite seats by its connection geometry, never by its drawn box: the centre of the terminals a part carries, the one connection point a label is, the whole run of trace a net run draws (16.4). A symmetric two-terminal symbol’s port midpoint is its box centre, so nothing moves; a flag drawing its name beside its symbol stands the symbol on the lattice line and lets the text hang off, which is what a sheet draws. Seating such a part by its box would put its wire half a name off the line the wire belongs on, which is ink deciding where a wire goes.

Anchors ride tracks. Anchors take the scope’s track grid: one row by default, in declaration order; columns: N wraps; cell: c r places explicitly. Track indices are ordinal — tracks spring into existence up to the largest referenced index and empty tracks collapse entirely, so sparse indices (10, 20, 30…) are safe ordering room and never inject invisible space. This is the engine’s own track list; it does not alter the grid layout’s laws (SPEC 12). A track sizes on the fine grid, to what stands between its anchors and the next track’s: the earlier’s field on the side they face, a span’s cells between them, the later’s field, and the corridor the two keep — a fine pitch of air per wire crossing it, one at the least, so a sheet with more traces between two parts spaces them further — never closer than a pitch of air between their bodies, nor than one coarse cell centre to centre. Satellites consume room, never tracks.

A chain is a walk. A satellite chain — the run of satellites one wire holds — takes a ray, a lane, and a slot per member:

• its ray is the growth direction, and the chain’s own members state it: every member presents the terminal its wire enters back up the ray, so the first member from the pin whose facing is already fixed decides — a part turned by an explicit rotate:, else the terminator’s own drawing (a |gnd|’s connection point sits at its top, so its chain grows down; a power flag’s at its bottom, so up). With nothing stated the chain runs straight out along the pin’s normal. A ray anti-parallel to that normal yields to it, the terminator posing inverted as a sheet flips a ground above a part. A pin’s straight corridor belongs to the wire running through it — one on to another placed part — so a chain sharing such a pin turns onto the canonical ray: down off a side pin, rightward off a top or bottom one. A chain of bare net runs is exempt, being that very trace named (16.4).
• its lane is the cross coordinate: a line out from the anchor’s ink for a chain that turned off its pin, the pin’s own line for one that grew straight out and takes no lane at all.
• its slots carry the members: the first on the field origin, and each one after it on the first line past the one before. Centred, not hung — so a cap and a resistor off one bus share a body row, their leads differing by their own lengths.

The trunk is the walk from the pin to the terminator; a subtree hanging off a mid-trunk member is a branch, grown from its attachment as a sub-chain along the ray its own members state. A tap — a single symbol-label branch, the rail flag beside a junction — takes no slot, hanging off its attachment member along its own drawn convention and stepping aside when that points back into the trunk.

A cell is its content’s, and nothing steps by gap. A member’s cell is the fine bands — a pitch centred on each fine line — its drawing reaches into from its seat point, so it lies where the drawing lies: a ground’s hangs below its connection point, a flag’s reaches further on its name’s side. A part adds the rows its ref and value take across its ray, where the readout rule stands them (16.2) — a corridor part whose pair stepped whole to one side leaves the other side’s row to the next pin — except that a pair standing beside its body takes the coarse cell centred on the part’s axis: text width never places, that room is the one thing gap states, and it is the one rhythm a column of parts keeps. Along its ray a part takes its symbol’s length and a fine pitch of air; a label, being its own terminal and no part (16.4), takes only what it draws, either way. So a no-connect cross grown out of one pin leaves the pins either side their own rows, a net run takes exactly the line it lands on, and two bare returns off one connector stand a fine pitch apart where two resistors stand a whole column. A chain’s cells run from its own pin’s line out to its outermost member, which is the column it really draws: a wire’s width (one fine pitch) from the pin’s line to the first cell, the cells from there.

Every line the field picks is then found by stepping one fine line at a time until the cells clear, and never by a pitch stated in advance: a lane is free when no cell of the chain meets one already committed and its wire — one pitch wide, down its line to its last member — runs through no ink a seated member paints, and a taken lane steps out a fine line and tries again; a member stands on the first fine line past the one before it. So a value overhanging its coarse cell pushes no part, only the wire that would otherwise cross it. That is why two stacked discretes still stand a coarse pitch apart — their cells say so, and a wire between two bodies any closer has no track — while a ground ends a chain a step under the part above it. A chain’s lead — the run from its pin out to its lane — reserves nothing, the lane order keeping it clear. So four things need no rule: an up-chain and a down-chain off one pin share a lane, their columns meeting at exactly the one line; two pins whose rays point at each other take a lane each, both claiming the band between them; a second chain claiming a pin’s straight corridor steps beside it, theirs being the same cell; and no chain lands where a lead must cross.

Lane order is the pins’ own. A pin’s column is live above its row where a chain climbs off it and below where one drops, and a lead crosses every inner column live toward its pin — so the lanes go innermost first to the pin whose column the fewest other leads of the side would cross, a pin’s up- and down-chain allotted together, ties to the pin deeper along the canonical direction (down, right), then statement order. On a one-way side that is depth along the ray; a side carrying both rays crosses only where an upper pin’s return must drop past a lower pin’s rail, on the rail’s lead. The chains that grew straight out take no lane and compete for none, so they stand first: they are the geography every lane then steps past — except a part-led one sharing its pin with a turned chain, which grows after that pin’s lanes and past them, the junction on its own lead ahead of its first member. A chain led by a bare net run is exempt, being that very trace named. Chains off one pin take their lanes in their parts’ declaration order — bar a flag, a turned chain of one symbol label, which rides the outermost lane the pin’s other chains took where its cell fits there, so the rail closes over the whole run it feeds rather than ending between two of its columns.

A field starts where its cells clear the ink. The innermost lane on a side is the first line whose cells stand clear of the anchor’s own drawn ink there, readouts included — so a part’s cell edge lands on the body and no further out, and a chain carrying nothing but a ground symbol starts a fine pitch off it. The first slot clears what that chain’s own lead passes: a chain that turned into a lane is beside the body already — that is what the lane is — and clears the deepest wired pin of its side along the ray, so a lead crossing its column meets bare wire, never a body; one that grew straight out has its ray pointing through the body, and clears the ink. Every one of these is a separation, measured in ink and quantised to the fine grid: rounding a separation up to a coarse line buys a whole cell of bare wire for a shortfall of one unit.

A slot origin is the track line’s, not the anchor’s: every anchor riding the line across the ray — the same track row for an up or down ray, the same track column for a left or right one — shares one, the deepest requirement among them. That is what stands two anchors’ fields on one row, bar the alignment below, which carries an anchor and its whole field together.

Terminators end where they end. There is no ground row and no flag row. A chain’s last member stands a step under the one above it like any other, and chains of one depth therefore land on one line — which is the ground line a sheet draws when it draws one, and none when the chains differ, as every reference sheet has it. Aligning three power flags naming three nets would say nothing at all.

Facing pins align. Two anchors in one track row stand centre to centre on a shared row line, except that a wire — or a span, whose members all ride one line — joining a facing pin pair (an earlier column’s right pins against a later column’s left pins; columns mirror it) aligns that pair instead, and the wire draws dead straight. The shift is a whole number of fine pitches, so alignment never breaks the lattice, and it is struck before the tracks size, so an aligned anchor never overruns its allotment. Deterministic: anchors take alignment in track order, each through the first statement-order wire reaching a placed neighbour.

Two placed ends. A chain held at two different anchors is a span: its members ride the wire’s landing leg — the straight run into the second end, on that pin’s own line — on consecutive coarse cells, the last-named nearest that end; the region between the two tracks holds the earlier anchor’s right lanes, then the span, then the later’s left lanes. A chain whose ends are two terminals of one anchor is a bridge (U2.EN - R5 - U2.VIN): it grows off the first-named pin like any one-end chain, whichever sides the two pins take, and the far wire is the router’s, merged into the second pin’s net at a junction dot. Pins on one side make that wire’s way home the second pin’s own row. A chain it taps mid-way — the far wire landing on a later member’s entry pin — straddles that row where the members before the junction fit above it: they take the chain’s own origin, since a wire ending on the chain is no lead it must clear, the tapped member stands past the row, and the tap comes home dead straight to the junction leg (the feedback divider, tapped between its two resistors); with no such room the chain clears the row like any lead. A member lying along the row instead steps its ref and value clear of it rather than straddling (16.2): left on it they wall the return off, and a wire that must land on a port and cannot tee into its net can then only orbit the member’s body. A chain distributes between two ends and no more, so a third placed end is named and dropped; a chain with no placed end falls back to the flow. Both warn (SPEC 21).

A seated satellite registers as a router obstacle like any node. cell: promotes a satellite to an anchor; translate: nudges it from its seat (pin-relative — move the component and the nudge travels along, SPEC 5).

Pose is rotation. Every schematic part has authored connection geometry — pins on parts, one connection point on a label symbol. A satellite auto-poses to the 90°-step pose that presents its terminal back up the chain’s own growth ray (deterministic tie-break: the unrotated pose, then clockwise) — so a ground, which sets that ray from its own drawing, is never turned, and a part in the middle of the chain stands to meet it. An explicit rotate: 0 | 90 | 180 | 270 forces the pose, and so states the ray for the chain it stands in (above): a resistor stood with its entry pin at its bottom grows its chain up, the unforced members turning to follow. mirror: x-axis | y-axis flips the part about its own axis first, the turn coming after — the axes named as the pen names them (15.3): y-axis swaps left and right, so a header faces the other way with pin 1 still on top, and a transistor swaps the side its collector points to. A flip is never chosen for a part — the chooser turns it, the flip riding along. Either is read at lowering — pins re-side, the symbol re-lays, and every text (ref, value, pin names) stays upright, bar a net name, which reads along its run (16.4) — never as a paint transform; any other angle or axis is an error (SPEC 21).

16.2 Components & pins

|component#U7| "TMC2300-LA-T" [
  |pin#VS| { number: 18 };  |pin#STEP| { number: 4 }          // auto — the bilateral split
  |pin#nstdby| "VIO/NSTDBY" { side: right; number: 11 }
]
U7.VS - c24.p1 "VM"

|component| is the generic pin-bearing box — an IC, a module, a relay. Its smart label is the part name / value; its [ ] holds |pin| children. Pins without a side: split bilaterally — the first ⌈n/2⌉ on the left, the rest on the right, declaration order top-to-bottom (the ⌈n/2⌉ split of SPEC 12’s bilateral tree, mirrored — a component reads left-to-right); side: left | right | top | bottom overrides, and explicitly-sided pins are excluded from the split count. Pins lower into generated anonymous side rails — scope-transparent (SPEC 9), so U7.VS resolves with no rail in the path — one pin-pitch apart along the rail they landed on.

A pin’s smart label is its name, displayed inside the body; with no label the pin’s id is displayed — schematic identity is drawn, the way a |hole| draws its centre marks — and the label form covers names that can’t be ids ("VIO/NSTDBY", "1.8VOUT"). number: draws the pin number outside, beside the stub — the short lead the pin extends outward; the wire lands on the stub tip, departing outward along the pin’s side. Pin anatomy — stub, name, number — folds into the component’s own routing obstacle, and a pin’s translate: slides it along its side — a cross-axis component is an error (a pin lives on its side). A |space| among the pins is one empty rail slot — a fine pitch of air, the gap a datasheet draws between pin groups — on the rail of the pin written before it (a leading one, of the pin after it), or of its own side:; span: N makes it N slots. It is no pin, so the split never counts it, though the odd-slot rule below does. A single-pin component is legal (a test point, a mounting pad); an unwired part needs no id at all. |pin| the type and pin: the out-of-flow property (SPEC 5) are one word in two roles — never ambiguous: a type lives in bars, a property before a :.

The id is the reference designator. A component or discrete displays its id verbatim (#U7 reads “U7”). An anonymous part mints a display ref — prefix from its type (|R| → R1, R2…, IEEE 315), prefix: overriding (|ic::component| { prefix: "IC" } mints IC1…), declaration order, skipping authored names. A minted ref is display-only, never an endpoint — wiring R1.p1 to a minted ref is an unknown endpoint (SPEC 21): don’t care → free numbering; wire it → name it. Ref/value text places by rule, never by search (SPEC 16.1): above a component, the ref over the value, the pair clearing the top rail — stubs and numbers — where pins landed there. A symbol-bodied part turned to stand across its row stands on its own wire, so its pair steps beside the axis and reads its side off the field it is seated in — outward, away from the anchor (right aligned in a left field, left aligned in a right one, and right on neither flank); one lying along its row wears them above and below, centred — except where the anchor’s pins on that side crowd one way and leave the other free, when both lines step whole to the free side, the leading one keeping the line it had. A readout line stands further off a body than the one fine pitch the next pin’s row sits at, so a pair left straddling draws over a live row and closes the corridor the wire that needs it runs in (16.1’s bridge). A component’s pin rails seat so its pins land on fine lattice lines, whatever their count: a rail of an even count straddles its own middle, so it reserves the odd slot it is short of, and a part carrying only one of the two horizontal rails reserves the other, so its side pins keep the origin’s line. The outline then re-centres on the pins, so a reserved slot shows at neither end and the origin — the lattice point the pins count from — may sit half a pitch off the box’s middle. A pin off the lattice cannot be aligned to a neighbour’s (16.1), and the wire between them jogs.

|J| is the connector — a |component| define, prefix J, whose pins show numbers only; pins: N generates N numbered, nameless pins (|J#J3| "JST S4B-ZR" { pins: 4 }). A connector is one column, never the bilateral split: the generated pins are minted side: left, the header or terminal block standing at the sheet’s edge with its pins facing the circuit. rotate: 180 turns the column the other way (16.1), which is what a part on the left edge wants, and mirror: y-axis does the same with pin 1 still on top; authored |pin| children keep whatever side they state. |opamp| is the amplifier triangle — prefix U, pins out, inp, inn, its power pins present but hidden by default.

16.3 Discretes

One-, two- and three-terminal parts drawn as symbols (IEC), each with generated pins — so c24.p1 works with zero authoring — and its ref family as its type name:

The smart label is the value (|R#R18| "470m"); symbol: picks the variant — one knob for every family, and it sets the pin ids where they are semantic (d3.a, q1.b, q1.g per variant, bt1.plus). Polarity in a wire is a pin path (vm - |D|.k - x — cathode first). Orientation is rotate: (16.1).

A two-terminal symbol’s two leads are one line, and that line is the symbol’s own centre line: a drawing that lies to one side of it — an inductor’s coil, a polarized cap’s plus mark, a switch’s blade — reserves the side it does not use, exactly as an even pin rail reserves the slot it is short of (16.2). A part’s cell is centred on its lattice point, and so is the pair naming it, so a lead off that centre would hang both to one side of the wire they belong to. A three-terminal symbol’s two same-side pins straddle that line by a whole fine pitch each, so they are lattice lines too, and whatever rides one of them (16.1’s span, a facing pin aligned to it) lands on the grid exactly as it would on a component’s rail.

A symbol’s pin-to-pin length is no whole number of fine pitches, and at the default gap it cannot be: two parts stacked one coarse pitch apart leave gap − length between their bodies, and the router wants a clearance either side of the wire joining them, so the length falls short of the pitch it would need. Nothing asks it to be whole. A two-terminal part’s wire leaves along its own axis and turns on the line its centre stands on — a coarse line, and so a fine one — which is the line the track runs on; the pin’s own coordinate along that axis is where a wire ends, never a track it travels.

16.4 Labels

Components have pins; a label is its own terminal. |label| is the net tag: its smart label is the net text, drawn in the tag outline; shape: picks the outline — plain (default, no outline at all) · left · right · both (a flag, one or both ends drawn to a point) · round (a stadium) — the shapes are visual, not semantic (the conventional readings — output, input, bidirectional — are the reader’s, as a sequence’s -> vs --> are); symbol: swaps in a drawing from the schematic symbol set — gnd · earth · chassis · power · nc · antenna — text beside it like an icon’s, never under it: the symbol’s own edge is the label’s connection point, and the wire arrives there. Text alone is a net label, a symbol alone a ground, symbol + text a power flag. |gnd| and |nc| ship as built-in defines; a power net is a one-line define with intrinsic text (SPEC 8):

{ layout: schematic; |vm::label| { symbol: power } [ "VM" ] }
c24.p2 - |gnd|
U7.VS  - |vm|

A label has no pins and no dot-path; a wire lands on its connection point — a fixed port like a pin’s. :side is an error on every terminal, pin or label — a terminal owns its connection geometry.

A plain label is a run, not a stop. The two shaped readings are bodies the wire ends on — an outlined tag, a symbol — but a sheet writes a bare net name beside a stretch of trace, and shape: plain with no symbol: draws exactly that: the label’s box is a run of wire, its connection point the end away from the pin, so the router draws one wire the whole length of it and the name ends up over a trace. The run is net-label-run long (SPEC 10.5) and grows for a longer name — the ordinary width floor (SPEC 5), so |label| { width: N } raises it. Being a run and not a body, it is no obstacle: its frame is that landing line alone, and its text obstructs nothing, exactly as a link label does not (SPEC 9).

A name on a wired pin rides the wire. A text label wire (U8.BRA - "RS_A") on a pin another statement wires (U8.BRA - R20 - |gnd|) mints no run: its text becomes that wire’s net-name label — the two-ended spelling U8.BRA - R20 "RS_A" (16.5) — on the hop touching the pin of the first other statement naming it, its side: riding along. A shaped tag still draws its body; a declared |label| stays a run.

A no-connect cross is a mark, not a member. |nc| stands with its connection point on the first fine line at least one fine pitch past the stub tip, and shares no slot row (16.1).

Net text stands off its wire, never on it. The name sits a constant net-label-offset clear of the centreline — a schematic wire is never cut (16.5). Which side:

side: left \| right \| top \| bottom forces it — on the |label| for the minted run, on the wire statement for the two-ended form (u7.vs - c24.p1 "VM" { side: bottom }), one more owner of the side homonym (SPEC 17). A run poses like any part (16.1), read at lowering; its name is the one text a sheet turns, a name belonging to its trace as a label does to its body.

16.5 Wires

A schematic wire is an ordinary link, routed by the orthogonal router (ROUTING.md) with the scope’s dress: ends land on fixed ports (stub tips, label connection points), corners bend square (corner-radius: 0, the scope’s link default — SPEC 17), and a junction dot — generated |junction| chrome — marks every point where three or more wire ends meet (a fan’s trunk split, a shared pin). A plain net run’s lead never counts — the run’s box is the trace it names (16.4), so that wire is the one being named, not a second conductor leaving the point; every other terminal’s lead counts, so a rail forking to its power flag and its decoupling cap is dotted where it forks. Crossings stay clean and dotless. The wire laws:

• Pinless landing gates on arity, never on a type list: a wire to a 1-pin part lands on it; to a 2-pin part, on the next free pin in the type’s pin order (both taken → an error naming one); to a 3+-pin part it is an error suggesting a pin. Dangling pins are legal — |R| -> a lands p1, p2 stays open.
• A chain passes through a 2-pin part: the named (or next-free) pin is the entry, the other pin the exit — vm - |R| - |LED| - |gnd| is a series circuit in one line; vm - |D|.k - x enters at the cathode and exits at the anode. This law is the one carve-out from the chain equivalence (SPEC 9, SPEC 19): two statements naming one pin are a junction there, not a pass, so a schematic chain lowers cut only where the pass-through resolved (both pins written down) and one whose landing the scope cannot see stays a chain — only the chain itself still says what it means.
• Duplicates error — a repeated endpoint pair means nothing on a sheet; and same-pin landings merge into one implicit fan at the shared port, drawn as one lead until the split, dotted there.
• No implicit auto-create. A bare unknown id never mints a box in a schematic scope — the error suggests the quoted form: `did you mean
  • “NSTDBY” (a net label)?`. Declaration-at-first-use is the typed capsule (SPEC 9).
• A label wire is the one-ended form — the drawing-leader statement shape (SPEC 15.7) read by this scope: U7.DIAG - "NSTDBY" mints a |label| seated at the pin; the op’s end marker sets the label’s shape: (- plain, -> right, -< left, -<> both, -* round) exactly as an operator’s line sets stroke-style (SPEC 9); an explicit shape: wins. A capsule terminator (- |gnd|) is the symbol form of the same statement. A plain one on a pin another statement wires mints nothing: its text becomes that wire’s net-name label (16.4).
• Markers shape labels, nothing else: an op’s marker is legal only on a wire ending in a text-form label — a marked part-to-part wire, or a marker at a symbol-form label, errors. The op’s line stays free (-- is a dashed wire, plain stroke-style).
• A two-ended wire’s net name is its link label — U7.VS - c24.p1 "VM" — placed by along: as everywhere, then given the net-label convention whole (16.4): stood clear of the trace and inked --lini-label-ink, since a sheet carries no wire text but net names. Both spellings of one name therefore read alike. A shaped tag on such a wire is a separate label-wire statement at one of its pins.
• A sheet never opens a trace. The label knockout — a label riding its wire, the wire masked open behind it — is the diagram convention (SPEC 9); a schematic scope draws in the other one, standing the net name beside the line, so there is nothing to cut around. The law is the scope’s, not the placement’s: should a name ever fail to clear its wire, it overlaps a whole trace, which still reads, rather than punching a hole in one, which is a wrong drawing.

16.6 Look

The classic sheet is the default inside the scope, riding role variables (SPEC 10) so a theme retunes it: wires green, part bodies pale yellow with dark-red outlines, labels teal, pin numbers muted, the scene beige — each a light-dark() pair. The scope’s generated link defaults (SPEC 17): a thinner wire, the net tag’s ink, corner-radius: 0.

Opting into the engine is one decision. layout: schematic carries the scope’s own config — the lattice gap and that tighter clearance — wherever it is written: the sheet’s baked constants (SPEC 10.5) are tuned to it, so a scope routing at the diagram’s default would stray the leads it seats. |schematic| is the template (|block| + the layout, plus the sheet wash); a root { layout: schematic } works like every root engine; and |region::group| { layout: schematic } is a captioned block that seats its own parts, keeping its own paint — its label a |sheet-caption| (SPEC 8), inside the frame as a sheet titles a block. Groups, pages, and title blocks are the core types, restyled by scoped rules.

16.7 Lowering

layout: schematic resolves in the layout phase (SPEC 19): desugar has already lowered components into rails and chrome, minted label wires and capsule declarations, and emitted the scoped look rules; the engine then assigns every satellite its cell (ray, lane, slot), packs the tracks on the fine grid, absolutizes the seats, seats the readouts, and hands every wire — with its fixed ports — to the router. Junction dots are read off the routed geometry and emitted as |junction| chrome. The scope’s links stay ordinary routed links and its children arrange in place — no subtree is consumed; only the generated chrome (pin rails, readouts, tags, junctions) is new.

Canonical, dense lookup. The narrative (Parts I–II) teaches once; this part is the authoritative tables — every property, the output, the pipeline, the grammar, the errors — and never repeats the prose.